Memory Map:

Here's a summary of the address ranges from the provided document, organized into tables for clarity. Note that some ranges overlap due to the use of different target numbers within the AHB bus. The overlapping addresses would not function simultaneously. The document also indicates some ranges are configurable.

1. RISC-V Core Memory Map Address Regions

Subsystem Address Size Start Address End Address Description
ROM 48 KiB 0x0000_0000 0x0000_BFFF Read-only memory
Cryptographic 512 KiB 0x1000_0000 0x1007_FFFF Cryptographic IP blocks (see detailed table below)
Peripherals 32 KiB 0x2000_0000 0x2000_7FFF Peripheral IP blocks (see detailed table below)
SoC IFC 256 KiB 0x3000_0000 0x3003_FFFF SoC Interface components (see detailed table below)
RISC-V Core ICCM 128 KiB 0x4000_0000 0x4001_FFFF Instruction Cache Memory
RISC-V Core DCCM 128 KiB 0x5000_0000 0x5001_FFFF Data Cache Memory
RISC-V MM CSR (PIC) 256 MiB 0x6000_0000 0x6FFF_FFFF Machine Mode Control and Status Registers (Machine-mode interrupt controller)

2. Cryptographic Subsystem Memory Map

IP/Peripheral Target # Address Size Start Address End Address Description
Cryptographic Initialization Engine 0 32 KiB 0x1000_0000 0x1000_7FFF Initialization logic
ECC Secp384 1 32 KiB 0x1000_8000 0x1000_FFFF Elliptic Curve Cryptography
HMAC512 2 4 KiB 0x1001_0000 0x1001_0FFF HMAC-SHA512
Key Vault 3 8 KiB 0x1001_8000 0x1001_9FFF Key storage
PCR Vault 4 8 KiB 0x1001_A000 0x1001_BFFF Platform Configuration Register storage
Data Vault 5 8 KiB 0x1001_C000 0x1001_DFFF Data storage
SHA512 6 32 KiB 0x1002_0000 0x1002_7FFF SHA-512 hash function
SHA256 10 32 KiB 0x1002_8000 0x1002_FFFF SHA-256 hash function
ML-DSA 14 64 KiB 0x1003_0000 0x1003_FFFF Module-lattice Digital Signature Algorithm

3. Peripherals Subsystem Memory Map

IP/Peripheral Target # Address Size Start Address End Address Description
CSRNG 12 4 KiB 0x2000_2000 0x2000_2FFF Cryptographically Secure Random Number Generator
ENTROPY SRC 13 4 KiB 0x2000_3000 0x2000_3FFF Entropy Source

4. SoC Interface Subsystem Memory Map

IP/Peripheral Target # Address Size Start Address End Address Description
Mailbox SRAM Direct Access 7 128 KiB 0x3000_0000 0x3001_FFFF Direct access to Mailbox SRAM
Mailbox CSR 7 4 KiB 0x3002_0000 0x3002_0FFF Mailbox Control and Status Registers
Mailbox 7 64 KiB 0x3003_0000 0x3003_FFFF Mailbox communication interface

5. RISC-V Core Local Memory Blocks

IP/Peripheral Target # Address Size Start Address End Address Description
ICCM0 (via DMA) 9 128 KiB 0x4000_0000 0x4001_FFFF Instruction Cache Memory (accessed via DMA)
DCCM 8 128 KiB 0x5000_0000 0x5001_FFFF Data Cache Memory

6. PCR Vault Memory Map

Register Address Offset Size Description
PCR Control[31:0] 0x1001a000 128B 32 Control registers, 32 bits each
PCR Entry[31:0][11:0][31:0] 0x1001a600 12288B 32 PCR entries, 384 bits each

7. Key Vault Memory Map

Register Size Description
Key Control[31:0] 128B 32 Control registers, 32 bits each
Key Entry[31:0][11:0][31:0] 12288B 32 Key entries, 384 bits each
No read or write access

8. De-obfuscation Engine Memory Map

Register Address Size Description
IV 0x10000000 16B 128 bit IV for DOE flow. Stored in big-endian representation.
CTRL 0x10000010 4B Controls for DOE flows.
STATUS 0x10000014 4B Valid indicates the command is done and results are stored in key vault. Ready indicates the core is ready for another command.

9. Data Vault Memory Map (Sizes are approximate and may depend on implementation)

This section describes the number of registers, not a contiguous address space. Exact addresses would need to be specified in a register map.

Register Type Number of Registers Size per Register Total Size (approx) Description
48B lockable (cold reset) 10 48B 480B Scratchpad registers cleared on cold reset
48B lockable (warm reset) 10 48B 480B Scratchpad registers cleared on warm reset
4B lockable (cold reset) 8 4B 32B Scratchpad registers cleared on cold reset
4B lockable (warm reset) 10 4B 40B Scratchpad registers cleared on warm reset
4B (warm reset) 8 4B 32B Scratchpad registers cleared on warm reset

Remember that this is a summary. For precise details, always refer to the latest revision of the official Caliptra hardware specification.

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  1. What is the total size of the RISC-V Core memory map, considering all listed subsystems and their potential overlaps?

  2. Which cryptographic subsystems utilize the largest and smallest address spaces within the 0x1000_0000 - 0x1007_FFFF range?

  3. How many 48B lockable registers are available in the Data Vault, and how do their reset behaviors differ?